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Thursday, May 28, 2015

Silicon Photonics in the Year of Light


https://www.youtube.com/watch?v=vIiqAcGr614
As we celebrate UNESCO's International Year of Light 2015, it is with some irony that earlier this month on May 12, 2015 IBM announced [1] it had fully fabricated and tested an integrated wavelength, multiplexed 100 Gb/sec silicon CMOS nano-photonic optical tranceiver chip whose design concept was first announced in December 2010 [2]. IBM's effort is echoed by consortiums of major players in the semiconductor industry, all in hot pursuit of silicon photonics [3] technology, and for good reason. The silicon photonics market is estimated to be worth $975 Million by the year 2020 [4]. Key players in this market include IBM, Intel Corporation and the CLR4 Innovators, PETRA (Japan's Photonics Electronics Technology Research Association), Hamamatsu Photonics, Finisar Corporation, Luxtera, Inc., ST Microelectronics, 3S Photonics, Oclaro Inc., Mellanox technologies, and Infinera Inc. The Optical Fiber Communication Conference and Exposition (OFC) [5] took place in Tokyo in March this year where many of these companies presented reports on their silicon photonic technologies.

IBM's recent announcement places emphasis on its compact device package and process proven fabrication techniques which will enable larger scale manufacturing of the devices for use in cloud computing and data centers in anticipation of “Big Data” network scaling. While IBM's most recent announcement is coincident with the International Year of Light, silicon photonics have been a glimmer in the eyes of semiconductor engineers for the past thirty years. In a recent SPIETV video presentation on silicon photonics, Yurii A. Vlasov of IBM [6] stated that during the past ten years over $1.5 B has been spent in the global quest for light based chip technology.  A portion of this investment resulted in an IBM silicon nano-photonic device design in which interconnected beams of wave guided light replace traditional electrical signals carried on copper circuit paths. Data carried by electrical signals on copper circuits propagate at only 66-70% of the speed of light as determined by dielectric properties near conductors and other physical factors. Device design engineers anticipated the day when this speed limitation would slow network server systems, as well as chip to chip intra-device data flow, and eventually singular on chip communications. To most smart phone owners, it's difficult to imagine a scenario in which electrical signals traveling at 66 to 70% of the speed of light becomes a limiting factor in computer chip design and performance, but in a world where global communications servers are linked by fiber optics, satellites and GPS navigation systems, cumulative device delay times have already created bottle necks in our global networks.

Interestingly, many original glass fiber optic cables transported light at about 70% of light's velocity in a vacuum.  New research and development in fiber optics and materials have resulted in the fabrication of optical fibers which can transport light at better than 99% of its vacuum velocity (186,282 miles/sec).  New silicon photonic devices are being optimized to provide maximum light velocity [7] while simultaneously implementing WDM (Wave Division Multiplexing) to maximize data speeds and throughput.  As such, silicon photonic devices might vary in performance as per the designs of their manufacturers.  

Why are silicon photonics important? I'll review some important observations I've made in my November 2013 blog article, “The Cloud of Nations” [8].

On a global scale we observe that in a vacuum, light travels approximately 186,282 miles per second and can circle the earth in 134 milliseconds (about one tenth of a second). If we consider the earth as a large computer, the continents might be compared to microprocessors interconnected by our global Internet, milliseconds apart. If we observe our immediate, personal photometric sphere of existence, we find that in one nanosecond light travels one foot. How precise must our world be?

Chip Level Clock Skew

In the metrics of semiconductors nanosecond measurements are woefully imprecise and we must calibrate metrology in picoseconds in order to measure the speed of data traversing millimeter sized computer chips. In the semiconductor industry we refer to differences in data arrival time on a computer chip as clock skew. On a real semiconductor device, electrical signals on copper conductors travel at approximately 66-70% of light speed. An acceptable clock skew range approximating 20 to 200 picoseconds (pico = 10^-12) usually provides acceptable device performance but this specification can vary across device types and circuit designs. For each tick of the chip's master system clock, billions of transistor gates must be switched on and off in precise unison. A microprocessor operating at a 2 gigahertz clock speed must have sufficient temporal uniformity across the device so that the arrival time of gate switching signals are all within an acceptable time window. If the switching signal's arrival time falls outside this window, the microprocessor and the program it's running will crash. Careful design considerations go into device fabrication technique and wafer processing to ensure product and performance quality. More information on computer chip clock skew can be found in the paper “Skew Variability in 3-D ICs with Multiple Clock Domains” [9] Hu Xu, Vasilis F. Pavlidis, and Giovanni De Micheli, LSI - EPFL, CH-1015, Switzerland Email: {hu.xu, vasileios.pavlidis, giovanni.demicheli}@epfl.ch

As clock speeds increase and device geometries decrease, the <10nm design node will pose additional technical challenges in device timing and data throughput. The evolution of light speed photonic interconnects for on and off chip communication will minimize concerns with clock skew across chips and networks as device structures shrink to critical dimensions (CD) <10nm and become stacked in dense arrays. As the integration of CMOS silicon nano-photonics matures, we may eventually see microprocessors, memory chips and 3D devices structured on photonics instead of conventional copper conductors. In the interim, IBM anticipates that the more immediate advantages afforded by silicon nano-photonic inter-chip speeds could dramatically improve cloud server/network performance, and advance its Exascale super computer initiative which could potentially perform over a thousand times the speed of currently available systems. While the initial focus of silicon nano-photonics targets network centers and cloud servers, the wider proliferation of the technology can profoundly effect our evolving Internet.

IBM's silicon photonic chip will address concerns across networks as four 25 Gb/sec optical tranceivers operating on as many different wavelengths will combine to provide a throughput of 100Gb/sec. Installed in server systems, these optical chips could dramatically improve data throughput, reducing network latency and clock skew by eliminating delays inherent in copper conductors found in servers and data center network interfacing. Using sub 100nm design rules (typically 90nm), electrical and optical device structures are formed on the same substrate to maximize efficiency. IBM estimates the device's bandwidth can accommodate the transfer of a high definition movie (approximately 1.5 to 2 Gigabytes) in two seconds.

To achieve maximum bandwidth over distance, most of today's data centers employ Vertical Cavity Surface Emitting Lasers (VCSEL) distributed on multi-mode optical fiber. Remotely located cloud servers have placed new demands on network resources as even larger bandwidths over greater distances are required. To illustrate the importance of IBM's initial 2010 achievement, note that IBM's on-chip silicon photonic wavelength multiplexing emulates the initial success of dense wave multiplexing utilized in early generation fiber optic networks, the major difference being that IBM has achieved this capability at the chip level.  Previous dense wave fiber optic implementations utilized bulky hardware to enhance long haul fiber optic bandwidth. In 1998, AT&T researchers transmitted 100 simultaneous optical signals, each at a data rate of 10 gigabits per second over a distance of 400 km utilizing dense wavelength-division multiplexing (DWDM) technology [10], allowing multiple wavelengths to be combined into one optical signal. This technique increased the total data rate on one fiber to one terabit per second. Although IBM's current silicon photonic chip design utilizes 4 discreet channel wavelengths providing 100Gbit/sec, data throughput is scalable and could be configured to accommodate many demanding applications. While IBM's silicon nano-photonic initiative is impressive, significant global competition is not far behind.

Intel's CLR4 Silicon Photonic Initiative

The silicon photonic initiative is also being pursued by Intel [11] who has helped form a consortium of companies to agree upon product designs and industry standards. The CLR4 Innovators [12] are an alliance of 27 companies inclusive of Intel, HP, Dell, MACOM and SEMATECH (see the above CLR4 link for a complete list).  In April 2014, Intel outlined its silicon photonic initiative in a presentation [13] which addresses the common requirements of the CLR4. The 100 Gb/sec silicon photonics under development utilizes 4X25 Gb/sec tranceivers which can span 1000 meters to link server centers.

Unfortunately, Intel's initiative was set back in February this year as a key component in its silicon photonic module did not meet specifications and quality control standards. [14] The new modules will not ship till the end of 2015 which means they won't be installed till early 2016. Intel's customers (and possibly CLR4 Innovator members) intending to integrate its silicon photonic technology are in a holding pattern till next year.


PETRA's Silicon Photonic Demonstration

Japan's Photonics Electronics Technology Research Association (PETRA), recently demonstrated [15] 100 Gb/sec transmissions over 300 meters using its silicon photonics device technology. The device's 5mm x 5mm package containing 4x25 Gbp/sec transceivers, can be expanded to 12 or more channels to obtain throughputs greater than 300 Gbp/sec.  This scalability enables accommodation of future demands and upgrades of installed network infrastructure.  


Silicon Photonic Research at IMEC

IMEC is also active in silicon photonic research. In February 2015 this year at the International Solid State Circuits Conference, IMEC and its collaborators released results of recent developments in their laboratories [16] demonstrating a 4x20 Ghz/sec wavelength division multiplexing hybrid CMOS silicon photonics tranceiver.  The larger global effort to standardize silicon photonic performance specifications sets the stage for future implementation over many platforms.


Silicon Photonics and The "Internet of Things"

Silicon photonics can assist us in resolving a potential net neutrality dilemma. Much has been debated regarding the FCC's recent adaption of a net neutrality policy which precludes Internet service providers from charging premiums for high speed commercial traffic on the web while intentionally throttling speeds on their networks. Conspicuous consumption of bandwidth by consumers is now the norm given HD and 4K video programming available on the web. If you travel frequently and patronize fast food establishments or coffee shops and use their complementary Wi-Fi systems, you become acutely aware of the limitations on available bandwidth. Many fast food restaurants preface their Wi-Fi login screens with disclaimers of suitability for a particular use, proclaiming “intended for text and email only” and “not intended for video streaming”. All too often, email and other essential services are slow when compared with Asian and European networks. The intentional throttling of Wi-Fi bandwidth often lowers video resolutions to “wax paper” quality. It's disheartening to see 1080P video rendered at resolutions below that of 1960s era analog broadcast quality. Will the FCC's net neutrality policy effectively address these concerns? Should the concept of net neutrality also accommodate the anticipated “Internet of Things” (IoT)? The IoT envisions the interconnection of “things” on the web to include household utility monitors, appliances, cars, watches, and any imaginable “thing” assigned an IP address. A few months ago I read a story describing hackers launching malware they had placed on someone's refrigerator sporting an on board computer. The fridge's door featured an HD flat screen providing an interactive family kiosk in the kitchen, but connected to the web it also kept malware in cold storage. Should ISP's be required to provide equal bandwidth and network routing for email, video conferencing, refrigerators and toasters? A humorous question, but if you're video conferencing from the fridge while snacking in the kitchen, net neutrality/equality for appliances becomes a pertinent IoT policy discussion. That said, the new IPv6 Internet protocol will provide an exponential increase in available URL's required for new email addresses, web sites and “things” attached to the web. Accordingly, the projected increase in Internet traffic can only be accommodated by enhancing routing systems and cloud services, ensuring network speeds are optimized and remain viable as global connectivity escalates.

In this regard we might agree that from both consumer and enterprise perspectives, silicon photonic solutions are long overdue and will enjoy rapid acceptance when available for shipment and implementation.

Closing Thoughts

- It will be interesting to track the evolution of silicon photonics as market demands are met with the delivery of Intel's technology to the CLR4 group of companies.

- IBM will seek to optimize its positioning in the enterprise markets, leveraging its silicon nano-photonics, cloud server infrastructure and possible ramp of MRAM technology for strategic product applications. IBM's advances could also provide “warp speed” for networks if additionally optimized with its fasp (TM) Aspera [17] file transfer platform.

- IMEC could leverage its own silicon photonic designs as its partnered R&D effort yields finished products ready for deployment.

- PETRA and its member companies have demonstrated competitive silicon photonic technology with the ability to scale for future throughput demands. 

- Possible additions to the silicon photonic market equation are prospects for more efficiently deployed Software Defined Networking (SDN) [18] which could reduce traditional hardware and infrastructure costs while enhancing network speed, efficiency and reliability.

- Lucent Bell Labs has introduced an ultra-dense network architecture designed for silicon photonics at the optical network unit. [19] A proof of principal experiment demonstrated an FDMA architecture providing up to eight 300-MBd 16QAM (Quadrature Amplitude Modulation) subbands providing a bidirectional data rate of 9.6 Gb/sec.

As silicon photonic infrastructure expands to enhance our global networks, we may eventually see the migration of this technology to microprocessor and memory devices for use in super computing and consumer products.  Congratulations to IBM, Intel and the global technology alliance members who are working to enlighten our future with photonics.

Please join me in supporting SPIE and the International Year of Light 2015 [20] (click on the icons below for additional site links).

Thomas D. Jay
Semiconductor Industry Consultant

Thomas.Dale.Jay@gmail.com 
www.ThomasDaleJay.blogspot.com
Thomas D. Jay YouTube Channel


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Corporate, private entities or publications referenced or linked in this article are the respective owners of their logos, trademarks, service marks, media content and intellectual property.  Unless otherwise disclosed, Thomas D. Jay has no financial interest in companies referenced in blog articles or other published media communications. No representation is made to either buy or sell securities. Opinions expressed by Thomas D. Jay are his own. Thomas D. Jay does not employ or otherwise utilize/authorize third party agents to express his opinions, represent his interests or conduct business on his behalf except where formally contractually designated.

Acknowledgements and Reference Links

[1] https://www-03.ibm.com/press/us/en/pressrelease/46839.wss
IBM Press release, IBM web site May 12, 2015

[2] https://www-03.ibm.com/press/us/en/pressrelease/33115.wss
IBM Press Release, IBM web site, December 1, 2010

[3] http://en.wikipedia.org/wiki/Silicon_photonics
Wikipedia

[4] http://electronics.wesrch.com/paper-details/press-paper-EL1GP94JCLEHH-silicon-photonics-market-worth-497-53-million-by-2020
WeSRCH web site, MarketsandMarkets press release uploaded May 27, 2015

[5] http://www.ofcconference.org/en-us/home/about/
OFC web site

[6] https://www.youtube.com/watch?v=KRY53sEXyNI
Yurii A. Vlasov, SPIETV, YouTube

[7] http://www.nature.com/nphoton/journal/v7/n4/full/nphoton.2013.45.html
Nature Photonics

[8] http://www.thomasdalejay.blogspot.com/2013/11/the-cloud-of-nations.html
ThomasDaleJay.blogspot.com

[9]http://infoscience.epfl.ch/record/173534/files/ISCAS_11_1.pdf?version=1
InfoScience web site, Hu Xu, Vasilis F. Pavlidis, and Giovanni De Micheli, LSI - EPFL, CH-1015, Switzerland Email: {hu.xu, vasileios.pavlidis, giovanni.demicheli}@epfl.ch

[10] http://www.fiber-optics.info/history/P3/
Fiber Optics History web site

[11] http://www.intel.com/content/www/us/en/research/intel-labs-silicon-photonics-research.html
Intel web site

[12] http://www.intel.com/content/www/us/en/research/intel-labs-clr4-adopter-listing.html
Intel web site

[13] http://www.intel.com/content/www/us/en/research/intel-labs-clr4-presentation.html
Intel web site

[14] http://www.pcworld.com/article/2879152/intel-delays-part-for-highspeed-silicon-photonic-networking.html
PC World web site, Agam Shah, IDG News Service
February 2, 2015

[15] http://www.ofcconference.org/en-us/home/news-and-press/exhibitor-press-releases/petra-demonstrates-low-power-silicon-photonics-i-o/
OFC website

[16] http://www2.imec.be/be_en/press/imec-news/imec-ugent-tyndall-silicon-photonics-transceiver.html
IMEC web site

[17] http://asperasoft.com/resources/white-papers/ultra-high-speed-transport-technology/?gclid=Cj0KEQjw1pWrBRDuv-rhstiX6KwBEiQA5V9ZoXa1_o6T48KX_XxsJ95irqG6EuLgXtaJmB7fkHAFaNsaAnzj8P8HAQ
IBM Aspera web site

[18] https://en.wikipedia.org/wiki/Softwaredefined_networking
Wikipedia

[19] http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6997998
IEEE Xplore web site


[20] https://www.youtube.com/watch?v=-R8jJ0wPM2Q
International Year of Light 2015, Official Trailer, YouTube

Thursday, April 23, 2015

A Defining Inflection in the EUV Continuum


https://www.youtube.com/watch?v=vIiqAcGr614An April 22, 2015 ASML press release [1] announced an agreement with one of its major US customers (believed to be Intel) to purchase a minimum quantity of fifteen of its NXE:3350B EUV lithography systems with two of the units slated for delivery year end 2015. Intel has previously invested over $4 Billion in ASML. Given the size of the order, it would appear that Intel will proceed with a large scale strategic commitment to EUV lithography for future production process nodes =<10nm, with a path to 7nm and smaller CDs.

Although financial details of the purchase were not released, a sizable capital equipment expenditure has been made after many years of delay and uncertainty in the EUV program. This purchase transaction represents a large scale, high profile commitment to what has been a capital intensive development program delayed by uncooperative laws of physics, semiconductor sector business cycles, and capital market dynamics. It seems that the semiconductor production road map has been sufficiently refined, concomitant with related process technologies, and that confidence has been restored in long term EUV/HVM convergence/insertion forecasting. Although Intel's eventual commitment to production EUV had been anticipated, the waiting game is over. The remaining field of industry players who have withheld their commitments to EUV might now be motivated to secure anticipated purchase positioning with ASML before delivery date extensions become a concern.

SPIE Advanced Lithography 2015 was likely a key catalyst triggering this defining inflection point as process experts from around the globe converged to announce new and encouraging breakthroughs in lithography and related technologies which have heretofore gated the EUV program. We might review some of the important observations and breakthroughs which comprise the critical mass of the inflection:


EUV Inflection Triggers
Probable Key Factors in Intel's EUV Decision

- While lithographers have entertained DSA and electron beam lithography as developmental candidates for 7nm scaling, given current evolution, only 13.5nm stepper/scanners can provide the image resolution and throughput required for both pilot line and future HVM.

- SEMATECH recently announced the development of a metal oxide based photoresist which reduces the EUV power output required for EUVL dosimetry (typically 15 – 20 mJ/cm2) to less than 2 - 3 mJ/cm2. [2] The new resist enables process development at reduced EUV power levels, but will not eliminate the future requirement for higher HVM source power. In the interim, it's possible that process solutions can be built around this low dose resist, enabling further, accelerated development of EUV HVM.

- During SPIE Advanced Lithography on February 24, ASML announced TSMC's confirmation that it had processed 1022 wafers in twenty four hours [3] on its NXE:3300B with a sustained source power of 90 watts. There is encouraging new data illustrating improved MTBF while sustaining EUV source operation at higher power levels.

- ASML has made significant over all progress in EUV development and has recently updated its time line for implementation of key milestones. ASML released many new updates on their EUV program at SPIE Advanced Lithography 2015 which were quite voluminous (see the post conference SPIE abstract summary).

- Obstacles to 7nm and future nodes have been addressed. ASML and Carl Zeiss acknowledged in an invited paper at SPIE Advanced Lithography 2015, that higher resolutions will require 60mJ/cm2 for half pitch nodes <8nm. [4] ASML's work with Carl Zeiss has produced an optical system with a numeric aperture (NA) of 0.55 vs. ASML's current EUV NA of 0.33. The higher NA system will require 500 watts of EUV power to achieve the estimated 60 mJ/cm2 dosimetry required for throughput of 150 wafers/hour. While this ASML/Carl Zeiss achievement paves the way for =<7nm process nodes, current R&D programs are also under way to provide a visible path to a >500 watt free electron laser EUV source, identifying one of the last major puzzle pieces in ASML's EUV endeavor. While ASML continues to refine Laser Produced Plasma source technology, the future availability of a >500 watt free electron laser EUV source remains a critical item on the agenda, and will probably gate the time lines of related programs.

- ASML has entered the pellicle business in the self interest of providing viable protection for EUV photomasks from particulate contamination. The polysilicon based pellicles are transparent to EUV with a one pass transmission loss approximating 14% and seem to exhibit sufficient durability for use in production. Previous uncertainty in EUV pellicle viability and availability have been resolved.

- As a key semiconductor industry supplier, Veeco Instruments has been successful in providing ion beam deposition tooling enabling EUV mask fabrication for advanced process nodes within acceptable defect limits. Defect free mask fabrication for advanced nodes has been a gating factor in the EUV program.

- Advancements in actinic inspection are progressing. Lawrence Berkeley National Laboratory's CXRO has been developing the SHARP EUV microscope in cooperation with SEMATECH . [5] A progress report on mask inspection was made at SPIE Advanced Lithography 2015. The SHARP EUV microscope is illuminated by an EUV synchrotron light source within the CXRO complex. The commercial availability of EUV obtained from free electron laser technology could enable the emulation of SHARP's capabilities given comparable optical and analytical performance.

- Future commercial availability of free electron laser EUV sources could also offset concerns gating the development of actinic inspection tools by KLA-Tencor and others. Given proper design, it's possible that a single free electron source beamline could provide EUV source illumination for both stepper/scanner clusters and in-line actinic inspection tools.

- Recent successes at TSMC with ASML's NXE:3300B EUV systems have prompted an additional order for two newer model NXE:3350B tools. As foundry commitments to EUV lithography continue, Intel has taken a major strategic step to ensure its competitive leadership positioning in the global wafer fabrication market.


No doubt there were many other considerations factored into Intel's EUV purchase decision. Ultimately the achievement and convergence of key process and equipment performance concerns have prompted a major commitment to both lithography and investment strategy over the longer term. In doing so, Intel has set a defining course for the semiconductor industry.


Please join me in supporting SPIE and the International Year of Light 2015 (click on the icons below for additional site links).

Thomas D. Jay
Semiconductor Industry Consultant

Thomas.Dale.Jay@gmail.com
www.ThomasDaleJay.blogspot.com
Thomas D. Jay YouTube Channel



http://www.linkedin.com/in/thomasdjay/


https://www.youtube.com/watch?v=vIiqAcGr614
www.npi.org











www.spie.org


https://youtu.be/-R8jJ0wPM2Q



















Corporate, private entities or publications referenced or linked in this article are the respective owners of their logos, trademarks, service marks, media content and intellectual property.  Unless otherwise disclosed, Thomas D. Jay has no financial interest in companies referenced in blog articles or other published media communications. No representation is made to either buy or sell securities. Opinions expressed by Thomas D. Jay are his own. Thomas D. Jay does not employ or otherwise utilize/authorize third party agents to express his opinions, represent his interests or conduct business on his behalf except where formally contractually designated.

Acknowledgements and Reference Links

[1] ASML press release 

Friday, April 3, 2015

Perspective on SPIE Advanced Lithography - San Jose, CA - February 2015

https://www.youtube.com/watch?v=vIiqAcGr614SPIE Advanced Lithography 2015 in San Jose, CA (February 22 - 26) has provided yet another window on the semiconductor engineering community's prowess and its progress in sustaining Moore's Law. SPIE [1] is the international society for optics and photonics. Among its global membership are thousands of scientists and engineers comprising the semiconductor industry's critical mass of expertise, driving innovation/collaboration in the research, development and manufacture of today's smart electronic products. Recently encountered barriers in physics have slowed the further development of photolithography, the prime enabler of the smaller/faster cost/benefit curve known as Moore's Law [2] (Gordon E. Moore, co-founder of Intel Corp.). The manufacture of ever smaller, less expensive transistors and computer chips has historically sustained the evolution of computer technology. In the face of daunting, capital intensive engineering obstacles, the industry is taking slow and deliberate steps to refine the methodology of semiconductor device fabrication at the atomic scale measured in nanometers and picometers. While some have declared Moore's Law inoperable below the 28nm node, others have yet to abandon what has become the semiconductor industry's philosophia perenis. The effort to enhance lithography resolution beyond 7nm has promulgated a multitude of research on a range of technologies which continue to evolve. The sheer momentum and continued investment in the on-going EUV (Extreme UltraViolet) lithography program have sustained incremental improvements in ASML's NXE:3300B/3350B series stepper/scanners. These ASML lithography systems provide proven hardware/software platforms with the uniformity and precision required for current and future process nodes. The progression of Moore's Law has traditionally optimized two critical concerns, reductions in transistor CD (Critical Dimension) feature size and the associated cost of computer chip manufacturing. ASML's NXE:3300B series EUV stepper/scanner with its unprecedented $130 Million capital footprint has enabled ever smaller transistor and circuit CDs, the caveat being a geometric increase in the cost of system ownership. The disruption of Moore's Law and its traditionally complimentary trend lines suggest a strategy enabling CD reduction and process optimization at any cost. It is hoped that increases inherent in current cost trending will eventually acquiesce to restore Moore's Law as we contemplate 7nm manufacturing and more traditional product margins. Historically, production ramping of new process technology lowers costs over time as critical production parameters are optimized and refined. Given current developments, we will likely identify derivatives of Moore's Law exhibiting logarithmic cost/performance trends as future EUVL process technology/throughput is assimilated in high volume manufacturing (HVM).

The EUV Program

In the months preceding SPIE Advanced Lithography 2015, ASML and its customer base made several important announcements regarding NXE:3300B performance upgrades which enhanced source power output. IBM and TSMC made separate announcements describing ASML NXE:3100B EUV source power levels operating at 40 watts. [3] Coincident with SPIE Advanced Lithography this year, ASML announced that in recent testing, one of their NXE:3100B/3350B series EUV systems sustained output power of over 90 Watts. Also newsworthy, Gigaphoton announced their testing of a high power EUV source operating at 100 watts at a 50% duty cycle. Although there have been demonstrable, incremental improvements in source power and uptime, the timely delivery of 250 watt+ EUVL for high volume manufacturing (HVM) remains behind schedule. TSMC continues to invest in the NXE:3300B series platform provided by ASML and has reportedly placed orders for two newer generation NXE:3350B series systems promising higher EUV source power. By maintaining its commitment to the EUV program, TSMC will be strategically positioned to provide its foundry customers with superior EUV lithography capabilities, perhaps at reduced HVM throughput. Continuing concerns with EUV are the node sensitive phenomena of shot noise, line edge roughness and image blur caused by high energy EUV photon interaction with photoresists.
 

Frequent industry discussion still concerns problematic high energy photons produced at wavelengths of 13.5nm and shorter as they often induce secondary electron emissions [4] which can activate the photoresist outside intended line patterning, creating image blur and pattern distortion. At 13.5nm, photon energies approximate 92 electron volts which can exceed the band gap energy thresholds of resists and other source component materials. Over time, this phenomena also degrades the reflectivity of Bragg cell mirrors, and other critical surfaces found in the high vacuum system and optical beam line. As lithographers anticipate ever smaller geometries, some have advocated a further reduction in stepper light source bandwidth to 6 or 7nm to further improve device and line pattern resolutions. Experiments conducted utilizing gadolinium oxide (Gd2O3) as a plasma source material, have produced peak BEUV spectra approximating a 6.75 to 7.2nm bandwidth (Beyond Extreme UltraViolet). The resulting photon energy at this wavelength approximates 200 eV (electron volts). These higher photon energies and their resulting increase in secondary electron/particle emissions can cause even more pronounced blurring of lithographic imaging. Thus, it would seem that any advantage afforded by shorter wavelength source emissions might be compromised by higher energy secondary emission phenomena unless engineers can qualify new resists and source materials. SEMATECH has been testing photoresists for outgassing and operation with EUV lithography. [5] These phenomena are consistent with any light source operating from 13.5nm through the x-ray spectrum. The observation here is that these concerns are valid for both Tin (Sn) based LPP (Laser Produced Plasma) at 13.5nm and HGHG FEL beam lines (High Gain Harmonic Generation Free Electron Lasers) which are being tested at wavelengths as short as 1nm. Even if free electron lasers can be adapted for use as an EUV source, the phenomena of secondary electron emissions from spectra =<13.5nm in wavelength will continue to challenge current and future process nodes.

To illustrate this observation, I will refer you to the PV Education web site (www.pveducation.org) where photon energies may be easily computed from spectral wavelengths. Follow the link to the photon energy calculator at: http://www.pveducation.org/pvcdrom/properties-of-sunlight/energy-of-photon. [6] The above web page features a calculator/algorithm which facilitates the computation of photon energies as derived from wavelength spectra. To the right of the page is a color graph which depicts the visible light spectrum, also extending to the Ultra Violet (above) and Infra-Red (below) the scale. The chart is interactive. Navigate your cursor up or down on the color scale with your mouse, select a color, and with a click, the embedded algorithm will retrieve the represented color wavelength (λ) and calculate the resulting photon energy in both (eV) and Joules. There is a similar calculator at the bottom of the page which permits manual entry of wavelength data further above and below the range of the color chart's scale. Note that when entering the wavelength data at the bottom of the page, λ must be expressed in μm. For example; 13.5nm must be expressed as 0.0135 μm. Thus, we can easily calculate that 13.5nm (0.0135 μm) = 91.837 eV equivalent photon energy. Assuming engineers might some day experiment with shorter wavelength x-ray regime lithography, a 6nm (.006 μm) and 1nm (.001 μm) wavelength would produce calculated photon energies of 206.633 eV and 1,239.8 eV respectively. I have cited these examples to illustrate the engineering obstacles we might encounter at these shorter wavelengths as current problems with secondary electron emissions and shot noise at 13.5nm (91.837 eV photon energy) remain problematic for energy/particle sensitive application nodes. Shorter wavelengths utilized for future x-ray regime photolithography [7] can present additional engineering challenges, requiring new, higher performance materials for photoresists [8] and source components operating in a high vacuum environment.

Note that the current price of the ASML EUV systems approximate $130M each as compared with $33.5M for ASML's 193nm steppers (approximate average price on 3/28/2015). On November 24, 2014, ASML announced that TSMC placed orders for two NXE:3350B EUV systems with delivery planned for 2015. ASML's installed base of NXE:3300B systems (inclusive of the two existing NXE:3300B systems at TSMC) are planned for field upgrade to NXE:3350B performance specifications. Given current pricing, the four NXE: 3300B/3350B systems at TSMC represent an estimated $520M capital investment and a significant advantage in the highly competitive semiconductor foundry market place.

In addition to securing high power EUV sources for lithography, lower cost, lower power EUV sources for actinic inspection systems will be required for future metrology. Actinic inspection is achieved with microscopy illumination at the stepper/scanner's exposure wavelength, ensuring the best replication of spectral test conditions. Imaging resolutions currently required for semiconductor lithography and actinic inspection microscopes are achieved utilizing state of the art illumination sources operating at wavelengths ranging from DUV (Deep UltraViolet, 193nm) and EUV (Extreme UltraViolet, 13.5nm) wavelengths. Diffraction physics at these wavelengths facilitate current lithography and metrology for state of the art device CDs (Critical Dimensions).

To date, semiconductor engineers have cleverly exploited these shorter, soft x-ray wavelengths (currently extending to 13.5nm) to better resolve nanometer scale line patterns and devices. The additional introduction of liquid immersion lithographic technique at 193nm (193i) has enabled the enhancement of numeric aperture specifications beyond the range of conventional optical systems. These break through performance improvements have been accomplished with “brute force” engineering, with ASML sparing no expense or complexity in achieving its current lithographic design specifications. ASML has achieved similar “brute force” success with EUV lithography as exemplified by its NXE:3300B and newly introduced NXE:3350B series stepper/scanners. That said, the “brute force” descriptor I've invoked is worthy of justification and illustration. ASML/Cymer EUVL sources utilize both a solid state pre-pulse and larger 20 kilowatt CO2 laser to vaporize a stream of micron sized Tin (Sn) particles which currently yields <100 watts of EUV light. For comparison, our friends at Lockheed Martin very effectively utilize a 10 kilowatt fiber laser to track and shoot down incoming missiles [9] with impressive results. I've often wondered what the target missile's EUV yield and CE might be (there's probably a tin component in its soldered circuits). I should note that I'm not advocating the militarization of our wafer fabs, but want to illustrate the “brute force” of the LPP (Laser Produced Plasma) physics required to supply current EUVL power levels. Within the NXE:3100B systems, the integration and function of the massive 20 kilowatt CO2 laser is transparent to the user and is an excellent example of how potential swords can be made into plowshares (or perhaps ASML
shares NASDAQ:ASML).

           Observations on Current Lithography Trends

- As we know, 13.5nm lithography currently provides superior image resolution, enabling the scaling of critical dimensions <14nm.


- 13.5nm EUV source power levels have been demonstrated from 40-70 watts at the stepper IF (Intermediate Focus) with 90 watt capabilities recently demonstrated; still insufficient for High Volume Manufacturing (HVM). More reliability testing is required.

- 13.5nm CD resolution might be extended =<7nm utilizing multiple patterning techniques, but again, higher EUV source power will be required. [10]

- During SPIE Advanced Lithography on February 24, 2015 ASML announced TSMC's confirmation that is had processed 1022 wafers in twenty four hours [11] on its NXE:3300B with a sustained source power of 90 watts. TSMC anticipates it will use its EUV lithography systems in production.

- In the past ASML has released engineering strategies for achieving higher EUV source power levels by optimization of pre-pulse laser targeting, laser pulse timing and tin source feed rates. [12] The wave form and pulse rate of the larger CO2 laser was also optimized for best performance. The most recent NXE:3300B improvements also reflect the achievement of better uptime and MTBF (Mean Time Between Failure), permitting limited production testing.

- TSMC has recently purchased two NXE:3350B series stepper/scanners which will incorporate EUV source power output improvements, presumably from enhanced lasers, a warm swap tin feed mechanism and increased Tin (Sn) energy conversion efficiency.

- During the week of SPIE Advanced Lithography 2015, Gigaphoton announced their testing of a high power EUV source operating at 92 watts [13] at a 50% duty cycle.

- Although there have been recent improvements in performance, 13.5nm LPP sources will probably exhaust viable power scaling at levels approaching 300 watts. Achievement of desired HVM MTBF goals utilizing Sn LPP at these source power levels may be very difficult to achieve and I suspect that further source power progress must await the availability of free electron laser technology currently under development. [14]

- SEMATECH recently announced the development of a metal oxide based photoresist which reduces the EUV power output required for EUVL dosimetry (typically 15 – 20 mJ/cm2) to less than 2 - 3 mJ/cm2. [15] The new resist enables process development at reduced EUV power levels, but will not eliminate the future requirement for higher HVM source power.

- The requirement for higher EUV power has become even more critical as ASML and Carl Zeiss acknowledged in an invited paper at SPIE Advanced Lithography 2015, that higher resolutions will require 60mJ/cm2 for half pitch nodes <8nm. [16] ASML's work with Carl Zeiss has produced an optical system with a numeric aperture (NA) of 0.55 vs. ASML's current EUV NA of 0.33. The higher NA system will require 500 watts of EUV power to achieve the estimated 60 mJ/cm2 dosimetry required for throughput of 150 wafers/hour. While this concept extends the viability of 13.5nm lithography, the delivery of a reliable 500 watt EUV source remains a critical item on the agenda, meaning the availability of free electron laser technology will probably gate related programs.

- ASML has made significant progress in EUV development and has updated its time line for implementation of key milestones. In November 2014, Frits van Hout, ASML's Executive Vice President and Chief Program Officer made a special Investors Day presentation on EUV. [17] ASML released many additional updates on their EUV program at SPIE Advanced Lithography 2015 which were quite voluminous (see the post conference SPIE abstract summary).

- Free Electron Laser technology currently under development should be capable of providing the required 500 watt HVM power levels at 13.5nm and beyond, [18] but would still incur the on-going problems associated with secondary electron emissions.

- Although viable technology, a compact Free Electron Laser source designed for semiconductor photolithography [19] will require several years to develop. The progress on EUV lithography has been slow, but the pieces of the puzzle are coming together fostering further accelerated development.

- ASML has entered the pellicle business in the interest of providing viable protection for photomasks from particulate contamination. The polysilicon based pellicles are transparent to EUV with a one pass transmission loss approximating 14% and seem to exhibit sufficient durability for use in production.

- Cymer recently introduced the XLR700ix as an upgrade to its existing 193 nanometer Deep Ultra Violet (DUV) argon fluoride (ArF) laser light source . [20] The upgrade reduces the sources bandwidth, enhancing the purity/stability of the 193 nanometer spectral line, providing sharper image resolution and extending the service/process life of ASML's 193 nanometer immersion steppers. The upgrade will enable 14 nanometer line width image resolution (and beyond) as required for future semiconductor process nodes. This upgrade in capability will provide an additional time line buffer, extending the process/service life of 193nm systems as 13.5nm source technology matures.

- On March 24, 2015 it was announced that among 19 other companies, ASML was selected as a preferred quality supplier by Intel Corporation for 2014 . [21]

- Advancements in actinic inspection are progressing. Lawrence Berkeley National Laboratory's CXRO has been developing the SHARP EUV microscope in cooperation with SEMATECH . [22] A progress report on mask inspection was made at SPIE Advanced Lithography 2015.

- Additional experimentation has been conducted on 7nm light source technology in the hope of further improving image resolution. 7nm light source spectra has been produced utilizing Gadolinium Oxide (Ga2O3) as an ionization source material. [23] Photons emitted from this plasma exhibit higher levels of photon energy approximating 206eV. Thus, photoresists and system hardware/materials utilized in stepper/scanner systems operating at this wavelength may require upgrading and additional MTBF evaluation. Preliminary experimentation with 7nm lithography has produced line blurring at the CD nodes tested due to secondary emission excursions and resist PAG cell activation beyond the boundaries of intended line patterns. Given the line blurring and increased secondary emission energies encountered with 7nm light source technology, work continues to optimize 13.5nm EUV with increased CE and power output [23a] as it currently provides a best case lithography platform when utilized with currently tested materials, resists and light sources.

- In related news, on March 9, 2015 NIST published an Article on improving the accuracy of X-Ray Wavelength Calibration Measurements. [24] This technique could improve the accuracy of the spectral analysis of x-ray regime light source emissions, providing optimal stepper/scanner resolving power and reducing out of band emissions (OOB). NIST's enhanced wavelength calibration accuracy will assist us in pushing the spectral boundaries of lithography.

- Alternative lithography experiments with Directed Self Assembly techniques have produced viable line patterns below 28nm, [25] but might not scale to nodes <7nm due to variations in CD uniformity and precision. Further development of DSA continues and test results must be well qualified prior to acceptance for use in HVM.

- Electron beam lithography is a process proven technology and has been historically used to fabricate lithography masks for 193nm and EUV process nodes. EBL also facilitates the fabrication of NIL (Nano Imprint Lithography) molds, and enables maskless DWEB (Direct Write Electron Beam) fabrication of wafers. EBL has better DOF (Depth of Field) than 193i and EUV lithography. With better DOF, resolution and electron beam spot size control, maskless EBL could be better suited for highly resolved 20nm and <14nm lithography. The eBeam Initiative recently discussed a mask makers perspective on the 10nm node. Chris Progler of Photronics discusses the eBeam challenges ahead. [26] Although recognized for superior resolution, the throughput limitations of ebeam as compared with stepper/scanner lithography have limited its acceptance as a production tool. While multi-beam array system designs can improve throughput, there has been no large scale adaption of ebeam lithography in production wafer fabs. Progress in ebeam lithography continues and David Moreno recently hosted Aki Fujimura, CEO of D2S in a spring edition of "Shot Talk" featuring eBeam Initiative news [27] discussing recent highlights from SPIE Advanced Lithography 2015. An informative BACUS round table discussion of the eBeam Initiative's 2014 year end survey [27a] results includes moderator Jan Willis of D2S, Tom Faure of IBM, Bob Pack of GLOBALFOUNDRIES, Noriaki Yakanamada of NuFlare, and Aki Fujimura of D2S.


Abbe Road

Given the obstacles we might encounter improving the available uptime of LPP (Laser Produced Plasma) sources and the further enhancement of image resolution, what alternative lithography methods might we consider? Let's discuss some fundamentals and set the stage for a new approach to lithography. In a brief review of classical optics, conventional optical microscopes are limited in resolution and are insufficient for use in state of the art semiconductor photolithography.

A fundamental barrier in achieving higher resolution in optical microscopes is termed the diffraction limit. In 1873, Ernst Karl Abbe calculated the diffraction limit of optical microscopes. [28] Abbe determined that the physical limitations of conventional optical microscopes limit resolution to a field of view approximating 200nm. In a scenario depicting multiple sample specimens having dimensions less than 200nm (for example: 10 particles, each 15nm in size), each particle would receive the same illumination from the microscope while simultaneously appearing in the 200nm field of view. Equally illuminated, particles of this size are difficult to discern individually as their combined reflectivity/luminance can obscure the presence of any singular particle within the field of view. In this example, a diffraction limited 200nm field of view often yields particle imaging which can appear as one large mass or cloud to the viewer. To overcome this obstacle, lithographers now use the shorter wavelengths of 193nm DUV and 13.5nm EUV to escape the diffraction limitations of visible light. Although vastly superior to visible light for high resolution imaging, EUV light introduces yet another set of challenges.


A Replacement for EUV?

To date, high energy EUV photons and resulting secondary electron emissions remain a problem for 13.5 nm lithography. Although we have successfully produced radiation hardened semiconductor devices for military and space craft applications, we have yet to develop process techniques to suppress secondary electron emissions during EUV lithography fabrication. An ideal lithography process would produce high resolution imaging <10nm while eliminating process induced shot noise, line edge roughness and image blurring induced by secondary electron/particle emissions. Recent new advances in two and three color lithography promise to provide such solutions and pose exciting new possibilities for the semiconductor fabrication community.
 

STED - Stimulated Emission/Depletion Lithography

In 1994 Stefan Hell, Ph.D. And Jan Wichmann developed an imaging technique called Stimulation Emission/Depletion Microscopy (STED) for which Hell was awarded the Nobel Prize in chemistry in 2014. Their goal was to achieve superior optical resolution by using a primary laser to selectively raise the energy state of luminous sample cells of interest (thus enhancing their visibility). A secondary laser at a different wavelength was used to deplete the energy state of adjacent luminous cells within the field of view (suppressing their optical visibility). The net effect is the enhancement of the microscope's target image without the simultaneous background illumination interference from adjacent sample materials. Dr. Hell describes this technique in detail in his 2011 SPIE Phonics West presentation, titled Nanoscopy With Focused Light – 2011. Dr. Hell's presentation can be viewed on SPIE TV's YouTube channel. [29] I highly recommend you review this excellent background presentation.



Periodic Structures Presents
Three Color STED-Like Lithography

Recognizing the potential benefits STED technique might bring to semiconductor photolithography, John Petersen, SPIE Fellow, began research on adapting STED technology for the wafer fab. [30] John's company, Periodic Structures, Inc. has secured research grant funding from the National Science Foundation, and previously, DARPA and is in contracted collaboration with the University of Maryland to develop working prototypes of two and three color photolithography resist materials. Using a Digital Micro Mirror Device (DMD) for imaging, (instead of a conventional photomask) two colored lasers have been used to image two color photoresist while using an interference lithography technique to facilitate activation/depletion exposures. In early February 2015, prior to SPIE Advanced Lithography, I spoke to John at length to discuss his plans for the conference. He indicated that a three color resist was under development and anticipated its availability in time for discussions at SPIE Advanced Lithography. As predicted, during the conference his colleague John Fourkas, Ph.D. of the University of Maryland announced the creation of the first class of three color molecular switches needed to fabricate photoresists for sub 10nm resolution lithography. Subsequent experiments are planned to utilize two photon exposures to determine what resolutions can be achieved utilizing thick films. Given success with thick films, experimentation will continue to include thin films and single photon lithography. As posted in the SPIE web site's News Room, Dr. Fourkas' recent article [31] states that the current record for STED feature size is 9 nm using 800nm light for two-photon excitation and 375nm light for deactivation. Using this technique, photon excitation initiating the chemical activation of patterned photoresist is accomplished with 800nm light while the surface areas adjacent to the line patterns are energy depleted using 375nm exposures. This technique effectively suppresses line blurring while enhancing image resolution. The use of these longer wavelength light sources negate concerns with secondary electron emissions typical of 13.5nm process nodes. Photon energies encountered at wavelengths spanning 375nm to 800nm approximate a few volts as compared with almost 93 volts encountered at 13.5nm. This technique holds promise to improve image resolution at a greatly reduced cost. Higher resolutions below 28nm can also be achieved utilizing proven double patterning techniques to achieve desired line pitch. However, in a double or multiple patterned process, the chemical activation of the two color resist sometimes sustains itself after the initial activation/depletion exposure and can limit process window time. Although the initial photo activation is prevented with a depletion exposure, subsequent, cumulative stitching exposures can increase the dosimetry adjacent to intended line patterns and can enlarge their critical dimensions. Thus, cumulative multi-patterned exposures can ultimately restrict the final attainable pitch to 50nm or larger. Fortunately, this phenomenon can be eliminated using a three color technique where one wavelength can deactivate the resist from a preactivation energy state (in essence turning it off) while another wavelength can reverse this process (a return to a preactivation energy state) and a third exposes it (inducing a resist activation energy state). The addition of this third wavelength can be made to eliminate this process phenomenon, thus extending capabilities to write smaller multiple patterned geometries without compromising image quality and extending resolution approaching 5nm half pitch. In further describing multi-patterned imaging on the PSI (Periodic Structures Inc.) multi-color DMD lithography system, John Petersen went on to make an important clarification. “It is not simply multiple patterning in the conventional sense because the stitching is done without removing the wafer. This is critical in terms of edge placement control, defects and throughput. We plan to use a technique developed by Mark Schattenburg at MIT to achieve edge placement accuracy of +/- 0.67nm”.

In microscopy, using Ground State Depletion, Stephen Hell has imaged 2.8nm features with visible/near-IR. Based on a Normalized Image Log-Slope argument . [32] it is anticipated that 7nm half-pitch patterning can be accomplished with a 405nm depletion wavelength while maintaining a NILS of 1.5. The systems numerical aperture (NA) is currently specified at .95, but due to the system's small field size, immersion lithography techniques are possible and are not limited to water allowing the numerical aperture to range from 1.3 to 2 (dependent upon the immersion material used). STED-like three color lithography for semiconductor applications promises to provide an elegant solution to many process concerns at greatly reduced cost.



Observations Regarding Multi-Color
STED-Like Lithography

- Unlike currently available EUV systems, multi-color light source power levels should be sufficient to effect required HVM throughput dosimetry (although there are additional throughput issues to be addressed).

- There could be a significant difference in cost between currently available DUV/EUV resists and anticipated multi-color resists.

- A multi-color STED-like lithography system will not require a high vacuum system to accommodate the light sources and will simplify the utilities and environment required to support the scanner.

- A multi-color lithography system as compared with DUV and EUV systems should provide superior uptime and MTBF.

- An optimized multi-color lithography system providing resolutions comparable with 193 and 13.5nm stepper/scanners should be significantly less expensive to own and operate.

- Multi-color STED-like lithography could also simplify the resources required for actinic inspection possibly utilizing STED microscopy techniques.

- The longer wavelengths utilized in multi-color lithography could facilitate the use of a broader range of materials in the fabrication of photoresists.



- The longer wavelengths utilized in multi-color lithography would eliminate concerns with high energy photons inducing secondary emissions and line blur in photoresist.

- Multi-color STED-like lithograpy could become a complementary technology enabling cost/benefits for specific applications in place of, or along side EUVL based systems.


Closing Thoughts

Of the many developments reported at SPIE Advanced Lithography 2015, I suspect major interest and emphasis are focused on resolving the remaining EUV lithography issues of power output, MTBF and next generation process scaling <10nm. Over ten years have passed since the inception of the EUV program and many unresolved issues remain challenging. With current pricing of EUV stepper/scanners estimated to be $130M, there is an on-going interest in exploring viable alternative technologies which might similarly achieve current and future process resolutions while sustaining the historic cost/performance trend lines established by Moore's Law. In my opinion, John Petersen and the Periodic Structures team have presented an excellent alternative technology featuring a multi-color STED-like enhanced photolithography technique. STED technique is an elegant approach to achieving current and future CD design goals as it simultaneously provides required high resolution lithography at optimal dosimetry levels while eliminating concerns with secondary electron emissions and induced line blur/distortions. The multi-color STED program at Periodic Structures is currently funded by grants from the National Science Foundation. Interested parties should contact John Petersen, SPIE Fellow, for additional information on the R&D effort there.

I'd like to thank John Petersen and the team at Periodic Structures, Inc. [33] for their time and gracious provision of reference information while I prepared this article.

Congratulations to the Team at SPIE and the multitude of its members who've together made Advanced Lithography 2015 another event of record in semiconductor lithography.
My closing thoughts on YouTube.
 

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Thomas D. Jay
Semiconductor Industry Consultant

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Acknowledgements and Reference Links

[1] SPIE 
SPIE web site.

[2] Moore's Law 
Link to YouTube, Gordon Moore - Behind the Ubiquitous Microchip, University of California Television (UCTV).

[3] IBM and TSMC made separate announcements describing ASML NXE:3100B EUV source power levels operating at 40 watts
Link to ASML web site.

[4] secondary electron emissions 
Link to Wikipedia

[5] SEMATECH has been testing photoresists for outgassing and operation at high energy photon dose levels
Link to SEMATECH web site.

[6] http://www.pveducation.org/pvcdrom/properties-of-sunlight/energy-of-photon 
Link to PV Education.org web site.

[7]  future x-ray regime photolithography
Link to Wikipedia.

[8]  photoresists
Link to Wikipedia.

[9] For comparison, our friends at Lockheed Martin very effectively utilize a 10 kilowatt fiber laser to track and shoot down incoming missiles 
Link to Lockheed Martin, YouTube.

[10] higher EUV source power will be required 
Link to SPIE Digital Library.

[11] ASML announced TSMC's confirmation that it had processed 1022 wafers in twenty four hours 
Link to ASML web site.

[12] optimization of pre-pulse laser targeting, laser pulse timing and tin source feed rates 
Link to SPIE Digital Library.

[13] Gigaphoton announced their testing of a high power EUV source operating at 92 watts 
Link to SPIE Digital Library.

[14] I suspect that further source power progress must await the availability of free electron laser technology currently under development.
Link to Thomas D. Jay’s blog article; Future FEL/EUV Strategy - The Light at the End of the Beamline

[15]  photoresist which reduces the EUV power output required for EUVL dosimetry
Link to SEMATECH web site.

[16] ASML and Carl Zeiss acknowledged in an invited paper at SPIE Advanced Lithography 2015, that higher resolutions will require 60mJ/cm2 for half pitch nodes <8nm.
Link to SPIE Digital Library.

[17] Frits van Hout, ASML's Executive Vice President and Chief Program Officer made a special Investors Day presentation on EUV
Link to ASML web site.

[18] Free Electron Laser technology currently under development should be capable of providing the required 500 watt HVM power levels at 13.5 nm and beyond
Link to SPIE Digital Library.

[19] a compact Free Electron Laser source designed for semiconductor photolithography 
Link to Thomas D. Jay’s blog article; Future FEL/EUV Strategy - The Light at the End of the Beamline

[20] Cymer recently introduced the XLR700ix as an upgrade to its existing 193 nanometer Deep Ultra Violet (DUV) argon fluoride (ArF) laser light source
Link to Cymer web site.

[21]  ASML was selected as a preferred quality supplier by Intel Corporation for 2014
Link to ASML web site.

[22] Lawrence Berkeley National Laboratory's CXRO has been developing the SHARP EUV microscope in cooperation with SEMATECH .
Link to SPIE Digital Library.

[23] 7nm light source spectra has been produced utilizing Gadolinium Oxide (Ga2O3) as an ionization source material.
Link to EUV Litho web site.

[23a] work continues to optimize 13.5nm EUV with increased CE and power output
Link to FOM ARCNL, YouTube.

[24] NIST published an Article on improving the accuracy of X-Ray Wavelength Calibration Measurements
Link to NIST web site.

[25] Alternative lithography experiments with Directed Self Assembly techniques have produced viable line patterns below 28nm
Link to SPIE Digital Library.

[26] Chris Progler of Photronics discusses the eBeam challenges ahead.
Link to eBeam Initiative web site.

[27] David Moreno recently hosted Aki Fujimura, CEO of D2S in a spring edition of "Shot Talk" featuring eBeam Initiative news.
Link to eBeam Initiative, YouTube.

[27a] An informative BACUS round table discussion of the eBeam Initiative's 2014 year end survey 
Link to eBeam Initiative, YouTube. 

[28] Ernst Karl Abbe calculated the diffraction limit of optical microscopes.
Link to Wikipedia.

[29] Dr. Hell's presentation can be viewed on SPIE TV's YouTube channel
Link to SPIETV, Stefan Hell, SPIE Phonics West, Nanoscopy With Focused Light – 2011.

[30] John Petersen, SPIE Fellow, began research on adapting STED technology for the wafer fab.
Link to John Petersen's Slide Share web site.

[31] Dr. Fourkas' recent article 
Link to SPIE news web site.

[32] Normalized Image Log-Slope argument
Link to Chris Mack's LithoGuru web site.

[33] Periodic Structures, Inc.
Link to Periodic Structures web site.

Related blog articles of interest
by Thomas D. Jay

September 2014
Future FEL/EUV Strategy - The Light at the End of the Beamline

August 2014
The EUV Continuum - Have You Seen the Light?

June 2014
Semiconductor Industry Markets in the Economic Hay Stack

March 2014
A Perspective on EUV Lithography Feb. 2014
The NIF Shot Heard Around the World

November 2013
The Cloud of Nations

August 2013
The SCRUM of All Fears 

January 2013